The invention relates to a circuit configuration for protecting terminals of integrated circuits, in particular CMOS circuits, in which bypass transistors are connected between the circuit terminals and supply potential terminals.
In the context of the invention, the term "terminal" includes not only inputs, outputs, and combined inputs/outputs, but also supply potential connections.
Circuit configurations of this generic type are known and are described in more detail below in the description of the drawings.
Experiments on which the invention is based have shown that using MOS transistors of unlike channel types results in dissimilar response behavior in the transistors and therefore in poor protection against electrostatic voltages, or ESD protection.